The use of automatic test pattern generation (ATPG) to generate test patterns for scan-based or partially-scan-based integrated circuits is quite common. The scan tests generated by a typical ATPG tool, however, can create switching activity on the integrated circuit that far exceeds the activity present during normal operation of the circuit. Excessive switching activity can be created when a scan test causes the circuit-under-test (CUT) to operate outside of its normal functional operation. Furthermore, excessive switching activity can occur during several stages of the testing operation. For example, excessive switching can occur when the scan chain is loading a test pattern, unloading a test response, or when its scan cell contents are updated during the capture cycles (for example, when the scan cells are clocked by one or more functional clocks). Abnormal switching activity can create an abnormal peak power dissipation, an abnormal average power dissipation, and/or undesirable supply currents. Excessive power dissipation can create hot spots that could damage the CUT. Furthermore, excessive peak supply currents can cause supply voltage drops that result in increased gate delays during testing. Such gate delays during testing may cause good chips to fail (for instance, to fail at-speed tests) and cause unnecessary yield loss.